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Mediaprocessors are programmable processors specifically designed to provide flexible, cost-effective, high-performance computing platforms for multimedia computing. Most mediaprocessors support data cache, DMA, or both on a single chip. We introduce a prefetching cache-based memory system that requires minimal programmer input, but can transfer data between processor and main memory as efficiently as a DMA controller. The data transfer is efficient for three reasons. First, it utilizes a prefetcher to tolerate main memory latency. Second, it transfers both input and output data in blocks to minimize page misses in the off-chip DRAM and sustain a high memory throughput. Third, a no-write-allocate write-miss policy is used to efficiently utilize main memory bandwidth. The simulation results show that our cache-based memory system, on average, reduces execution time by 54% compared to a baseline cache-based architecture. In comparison, the average execution time reduction of a DMA controller over the baseline architecture was 56%.

I presented an overview of my work at the Annual Industrial Affiliates Meeting of the University of Washington Department of Computer Science and Engineering. Here is the talk (PowerPoint 120 kbytes) (pdf 319 kbytes) and poster (pdf 281 kbytes) that I presented during the meeting. The poster was printed on 32 x 40 inch paper, but is still barely legible on a good legal size printout.

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Last Updated: June 16, 2004